A MIG slice on an H100, what is it and what is it good for?
MIG is NVIDIA's hardware partitioning feature that splits an A100 or H100 into up to seven isolated GPU instances, each with guaranteed SMs, memory, and bandwidth.
Imagine you rent a giant warehouse to three small businesses. If you just throw them all inside, they will fight over forklifts and parking spots. Instead, you build solid walls inside the warehouse and give each tenant a separate door and parking lot. You also meter the loading dock so each business gets a guaranteed share. Now they cannot starve each other no matter what. MIG does this for a GPU. It builds walls inside the chip. Each tenant gets a slice of compute units, a slice of memory, and a slice of bandwidth, so a noisy neighbor cannot slow you down. The walls are real silicon partitions, not software polite-sharing rules.
Concept explanation~2 min read
Everything you need to truly understand this topic: intuition, mechanics, step by step explanation, code, formulas, and worked example. Click to expand.
Concept explanation~2 min read
Everything you need to truly understand this topic: intuition, mechanics, step by step explanation, code, formulas, and worked example. Click to expand.
Multi-Instance GPU, or MIG, is the strictest way to share a single NVIDIA datacenter GPU between unrelated workloads. Older techniques like time-slicing and CUDA MPS let multiple processes use the same silicon but offer no real guarantees about fairness or isolation. MIG is different. It partitions the chip in hardware and gives each tenant a guaranteed slice of compute, memory, and bandwidth that no neighbor can use.
The price is rigidity. Profiles are fixed shapes chosen up front, slices cannot pool their memory, and tensor parallelism across slices does not work.
What MIG partitions
An NVIDIA datacenter GPU like the H100 has internal structure that most users never see. Inside the chip are several Graphics Processing Clusters (GPCs), each containing a fixed number of streaming multiprocessors (SMs). The HBM memory comes in stacks, and the L2 cache is sliced and tied to specific stacks. The memory bandwidth is the sum of what each stack can deliver.
MIG turns this internal structure into an addressable partitioning scheme. When you enable MIG mode, you pick a profile for a single GPU Instance (GI). The profile allocates some number of GPCs, a paired chunk of HBM, the corresponding L2 cache slice, and the bandwidth quota. Each GI is a logical GPU. It gets its own CUDA device UUID, its own driver context, and its own MMU. The hardware assigns each GI its own crossbar ports, L2 cache banks, memory controllers and DRAM address busses. The hardware blocks cross-GI memory access. Cache lines do not leak across slices. Bandwidth is partitioned by the memory controller, not just shared cooperatively.
The result is that two MIG slices on the same physical card behave like two separate, smaller GPUs. A workload running at full load on slice 1 has no measurable impact on a workload running on slice 2. This is qualitatively different from MPS or time-slicing, where the underlying hardware is shared and any guarantees are best-effort at the software level.
Situations where this technique stops working.
2–4 min · Everything important, quickly.
| Sharing mode | Isolation | Setup | Best for |
|---|---|---|---|
| MIG | Hardware-enforced (SMs, memory, BW) | Static partition, requires reconfig | Multi-tenant inference, strict SLAs |
| CUDA MPS | Shared memory and L2, no fault isolation | Runtime, on demand | Many small jobs from one team |
| Time-slicing | None, full context switch | Default behavior | Sequential workloads on idle GPU |
| Full GPU | N/A (sole tenant) | Default | Large models, training, tensor parallelism |
Real products, models, and research that use this idea.
- Google Kubernetes Engine can partition A100, H100, H200 and B200 GPUs into MIG instances. The partition size (for example 1g.5gb) is set per node pool, so several containers share one GPU.
- Multi-tenant inference platforms host several small models on one H100, each in its own MIG slice, so one customer's traffic spike cannot slow another's.
What an interviewer would ask next. Try answering before peeking at the approach.
QWhy is MIG limited to seven slices on an A100 or H100?
The chip's compute is split into seven slices (SMs in sevenths) and its memory into eighths, so the smallest profile can repeat at most seven times. The count is set by the hardware design, not by software. Newer cards may change the count, but the slice cap is a physical property of the partitioning hardware.
Red flags & common mistakes
The phrases that signal junior thinking. Click to expand.
Red flags & common mistakes
The phrases that signal junior thinking. Click to expand.
Thinking MIG is the same as CUDA MPS or time-slicing. MIG is a hardware partition with strict isolation. MPS shares memory and L2 cache with no fault isolation.
60 second bullets to scan on the way to the call.
Definition of MIG as a hardware-level GPU partition feature
Which GPUs support MIG (A100, H100, and successors)
Primary sources. Browse if you want the original framing.
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