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A MIG slice on an H100, what is it and what is it good for?

Flashcard·Easy·4.0 · 0·~30s·Asked atAmdCrestaMidjourney·Relevant atNVIDIA
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TL;DR

MIG is NVIDIA's hardware partitioning feature that splits an A100 or H100 into up to seven isolated GPU instances, each with guaranteed SMs, memory, and bandwidth.

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Easy to grasp

Imagine you rent a giant warehouse to three small businesses. If you just throw them all inside, they will fight over forklifts and parking spots. Instead, you build solid walls inside the warehouse, run a separate door and parking lot per tenant, and meter the loading dock so each business gets a guaranteed share. Now they cannot starve each other no matter what. MIG does this for a GPU. It builds walls inside the chip, gives each tenant a slice of compute units, a slice of memory, and a slice of bandwidth, so a noisy neighbor cannot eat your performance. The walls are real silicon partitions, not software polite-sharing rules.

Concept explanation~2 min read

Everything you need to truly understand this topic: intuition, mechanics, step by step explanation, code, formulas, and worked example. Click to expand.

Multi-Instance GPU, or MIG, is the most aggressive way to share a single NVIDIA datacenter GPU between unrelated workloads. Older techniques like time-slicing and CUDA MPS let multiple processes touch the same silicon but offer no real guarantees about fairness or isolation. MIG is different. It draws walls inside the chip and gives each tenant a guaranteed slice of compute, memory, and bandwidth that no neighbor can encroach on.

This deep dive walks through how MIG partitions an A100 or H100 at the hardware level, what profiles are available and how you pick one, how MIG compares against the other shared-GPU options, and where its rigidity becomes a real production constraint. By the end you should be able to argue for or against MIG for any concrete inference platform design.

What MIG actually partitions

An NVIDIA datacenter GPU like the H100 has internal structure that most users never see. Inside the chip are several Graphics Processing Clusters (GPCs), each containing a fixed number of streaming multiprocessors (SMs). The HBM memory comes in stacks, and the L2 cache is sliced and tied to specific stacks. The memory bandwidth is the sum of what each stack can deliver.

MIG turns this internal structure into an addressable partitioning scheme. When you enable MIG mode, you pick a profile that allocates some number of GPCs, a paired chunk of HBM, the corresponding L2 cache slice, and the bandwidth quota to a single GPU Instance (GI). Each GI is a logical GPU. It gets its own CUDA device UUID, its own driver context, and its own MMU. Cross-GI memory access is blocked by hardware. Cache lines do not leak across slices. Bandwidth is partitioned by the memory controller, not just shared cooperatively.

The result is that two MIG slices on the same physical card behave like two separate, smaller GPUs. A workload running flat-out on slice 1 has no measurable impact on a workload running on slice 2. This is qualitatively different from MPS or time-slicing, where the underlying hardware is shared and any guarantees are best-effort at the software level.

Profiles and the seven-slice cap
MIG vs MPS vs time-slicing
What MIG cannot do
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Situations where this technique stops working.

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2–4 min · Everything important, quickly.

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Sharing modeIsolationSetupBest for
MIGHardware-enforced (SMs, memory, BW)Static partition, requires reconfigMulti-tenant inference, strict SLAs
CUDA MPSCooperative, no quotasRuntime, on demandMany small jobs from one team
Time-slicingNone, full context switchDefault behaviorSequential workloads on idle GPU
Full GPUN/A (sole tenant)DefaultLarge models, training, tensor parallelism

Real products, models, and research that use this idea.

  • AWS, Google Cloud, and Azure all expose MIG-partitioned A100 and H100 instances as smaller, cheaper GPU SKUs (e.g., AWS g6e with a MIG-sliced H100).
  • Hugging Face Inference Endpoints uses MIG to serve many small models on shared H100s with strict per-customer isolation.
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What an interviewer would ask next. Try answering before peeking at the approach.

QWhy is MIG limited to seven slices on an A100 or H100?
A

Seven is the maximum number of independent GPCs in the chip's hardware partition table. The number is set by silicon topology, not by software. Newer cards may revisit the count, but the slice cap is a physical property of the partitioning fabric.

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Red flags & common mistakes

The phrases that signal junior thinking. Click to expand.

Most common mistake

Thinking MIG is the same as CUDA MPS or time-slicing. MIG is a hardware partition with strict isolation; MPS shares resources cooperatively with no enforced quotas.

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60 second bullets to scan on the way to the call.

  • Definition of MIG as a hardware-level GPU partition feature

  • Which GPUs support MIG (A100, H100, and successors)

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