Why is HBM bandwidth the binding constraint for LLM decode and how do you reason about the 'memory wall'?
Explain the 'memory wall' as it applies to LLM decode. Why does HBM bandwidth dominate compute? How is the gap evolving across GPU generations, and what optimization classes attack it directly?
The memory wall is the widening gap between compute growth and HBM-bandwidth growth; decode at low batch reads more bytes than it does math, so it is bandwidth-bound and worsens on newer GPUs.
Imagine a chef who can chop ingredients incredibly fast, but everything sits in a pantry down a long hallway. To cook one dish the chef sprints the hallway to fetch every ingredient, then chops it in seconds. The chopping is not the bottleneck, the hallway trips are. Every new kitchen model gives the chef faster hands but the same slow hallway. So cooking one dish at a time barely speeds up. The fix is to cook many dishes per hallway trip, or carry lighter ingredients. That hallway is memory bandwidth, the chopping is compute, and one dish at a time is decoding a single sequence. Reading the model from memory dominates, not the arithmetic.
Detailed answer & concept explanation~9 min readEverything you need to truly understand this topic: intuition, mechanics, step by step explanation, code, formulas, and worked example. Click to expand.
Everything you need to truly understand this topic: intuition, mechanics, step by step explanation, code, formulas, and worked example. Click to expand.
Everything you need to truly understand this topic: intuition, mechanics, step by step explanation, code, formulas, and worked example.
Everything important, quickly.
4 min: define the wall as compute and bandwidth divergence, derive arithmetic intensity, work the H100 70B weight-read versus arithmetic numbers, then map the four optimization classes onto the roofline.
Real products, models, and research that use this idea.
- vLLM uses continuous batching so a single weight read serves dozens of concurrent sequences, directly raising arithmetic intensity on decode.
- DeepSeek V4 ships Multi-head Latent Attention to compress KV cache reads, attacking the bandwidth side of the memory wall at long context.
- NVIDIA's H100 (3 TB/s) to B200 jump raised bandwidth far less than peak FLOPs, illustrating the widening gap the wall describes.
- Llama 4 and Mistral Large 3 ship GQA so fewer KV heads are read per token, shrinking the bandwidth bill on every decode step.
- TensorRT-LLM serves fp8 weights and fp8 KV cache on H100 and B200, halving bytes moved per token versus fp16.
What an interviewer would ask next. Try answering before peeking at the approach.
QWhy does batching help a bandwidth-bound workload so disproportionately?
QHow does speculative decoding move the workload along the roofline?
Don't say thisRed flags and common mistakes that signal junior thinking. Click to expand.
Red flags and common mistakes that signal junior thinking. Click to expand.
Treating decode as compute-bound and reaching for faster matmuls or more FLOPs. At batch 1 the GPU sits idle waiting on memory; adding compute does nothing until you raise arithmetic intensity.
The night-before-the-interview bullets. Scan these on the way to the call.
Primary sources. Skim if you want the original framing.
Same topic, related formats. Practice these next.