TPOT is high, so the team plans to upgrade A100 to a faster compute GPU, critique
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Decode is bandwidth-bound, so a GPU upgrade that doubles FLOPs while keeping HBM bandwidth flat barely changes TPOT. Per-step time floor = weight bytes / HBM bandwidth (~70ms for 70B bf16 on A100).
Picture a water hose filling a bucket. You can buy a much bigger bucket, but if the hose is the same size, the bucket fills at the same rate. The hose is HBM bandwidth, the bucket is compute. Decode keeps demanding the same big drink of data on every token; doubling the bucket size does not make the water arrive faster. To speed things up you need a bigger hose, like the H100 or B200, or you need to ask for less water, like switching to a smaller-bytes model with FP8 weights.
Detailed answer & concept explanation~9 min readEverything you need to truly understand this topic: intuition, mechanics, step by step explanation, code, formulas, and worked example. Click to expand.
Everything you need to truly understand this topic: intuition, mechanics, step by step explanation, code, formulas, and worked example. Click to expand.
Everything you need to truly understand this topic: intuition, mechanics, step by step explanation, code, formulas, and worked example.
Everything important, quickly.
3 min: compute the A100 TPOT floor (140 GB / 2 TB/s = 70 ms), show that doubling FLOPs at same bandwidth does not move it, list bandwidth-upgrade options with their floors, present FP8 as the zero-hardware alternative.
Real products, models, and research that use this idea.
- NVIDIA H200 release in late 2024 was pitched primarily on 1.4x HBM bandwidth (4.8 TB/s vs H100's 3.35) for inference, with FLOPs unchanged from H100.
- B200 in 2025 doubled bandwidth again to ~8 TB/s with FP4 tensor cores; FP4 weight reads on B200 deliver TPOT floors below 10ms even on 70B models.
- vLLM benchmarks on Llama-3 70B show single-stream TPOT scaling near-linearly with HBM bandwidth across A100/H100/H200, confirming the bandwidth-floor model.
- TensorRT-LLM FP8 path on H100 routinely delivers ~1.7-1.9x TPOT improvement for 70B models, matching the predicted bandwidth-bound scaling from halving bytes-per-step.
- Groq's LPU achieves >1000 tok/s single-stream on smaller models by pairing modest compute with extreme on-chip SRAM bandwidth and no HBM read at all; a direct empirical confirmation that bandwidth, not FLOPs, drives decode latency.
What an interviewer would ask next. Try answering before peeking at the approach.
QAt what batch size does a 70B model on H100 cross from bandwidth-bound to compute-bound during decode?
QHow does the KV cache contribute to the per-step bytes read, and when does it dominate?
Don't say thisRed flags and common mistakes that signal junior thinking. Click to expand.
Red flags and common mistakes that signal junior thinking. Click to expand.
Buying more compute to fix a decode TPOT problem. Decode is bandwidth-bound at batch 1, so additional TFLOPs sit idle waiting for HBM. The right upgrade adds bandwidth (H100/H200/B200) or shrinks bytes per step (FP8, GQA, MLA).
The night-before-the-interview bullets. Scan these on the way to the call.
Primary sources. Skim if you want the original framing.
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